Mentor Graphics Tutorial 2
Design Architect Transistor Level Schematic

Estimated Time: 1 hour

This tutorial uses Design Architect to implements the NOR gate using transistors and Eldo/EZwave to simulate the schematic. The length to width ratio we are using in this tutorial is 1:3. The width of the pmos to the width of the nmos for a nor gate is 4:1.

Note: It is a good idea to create a directory for each tutorial or part of a lab, and dedicate one subdirectory for the schematic and symbol, a second subdirectory for the testbench, and a third for the simulation. Do not move or rename directories.

Creating the Schematic

  1. Invoke Design Architect by typing ./daic from your home directory.
  2. To open a new schematic file click on 'File>Open>Schematic' on the Menu bar. Open Schematic window should pop up. (NOTE: If another schematic is open and the window is highlighted the File menu will not have the Open option. Unselect the window by clicking on the background if another schematic is highlighted.)
  3. Type in your folder of choice, and click on the 'Options' button. A new window pops up. Choose the New Sheet option, type in ‘nor’ as the Schematic, and click 'Ok.' A new schematics window should open.
  4. Click on the ‘Show/Hide Library Palette’ icon in the left panel if the Schematic Edit palette is hidden.
  5. Click on the ADK IC Library button in the Schematic Edit Palette.
  6. Add pmos, nmos, Portin, Portout, VDD and GND from the ADK IC Library.
  7. Connect the wires to complete the NOR gate as shown in the figure below.

    8. Fig: Completed NOR gate

  8. Name the nets A, B and Out.
  9. Change the width of the nmos transistors from the default value of 5 to 6. Right-click the nmos transistors and click on Properties>Modify and choose width. Change the value to 6.
  10. Repeat the same process to change the width of the pmos transistors to 24.
  11. Go to File>Check Schematic in the menu bar to check for errors. Correct the errors and ignore the warnings.

Making a Symbol for the Schematic

  1. Design Architect can create symbols from schematics. Go to Miscellaneous>Generate Symbol. in the menu bar.
  2. Keep the default settings. This will save the symbol in the directory with the schematic. You can change the Shape of the symbol generated by clicking Choose Shape. The default shape is a rectangle and we will go ahead with that. Click OK.

    3. Fig: Generate Symbol window.

  3. A new schematic with the generated symbol is generated. Note that there are no pins for VDD and GND. We will connect the inputs to VDD and GND in the testbench later.

    4. Fig: Nor symbol generated by Design Architect.

  4. Check the symbol by clicking File>Check Symbol. You should get 0 errors. Close the window that pops.
  5. Click File>Save Symbol. Close the symbol sheet.

Creating the Testbench

  1. Open a new schematic by clicking on File>Open>Schematic and browsing to a directory of your choice. (NOTE: If another schematic is open and the window is highlighted the File menu will not have the Open option. Unselect the window by clicking on the background if another schematic is highlighted.)
  2. Go to Add>Instance>Choose Symbol to insert the symbol we created from the schematic. Browse to where you have saved the symbol and choose it. Click on the blank schematic to place the symbol.
  3. Choose the ADK IC Library in the Schematic Edit palette in the right and place Portins (In) and Portout (Out) and connect the nets. Name the Nets A, B, and Out by Right-clicking the net and clicking Name Nets. Your schematic should look like the following.

    4. Fig: Testbench with the ports added and nets named.

  4. Our symbol does not have a VDD and the GND pin. We need to have connection to the VDD and GND so we place the VDD and GND from the ADK IC Library, and connect inputs to them. VDD and GND are globals and Mentor Graphics assumes that all VDD and GND are connected with other VDDs and GNDs. Extend the net one grid to make it easier to connect forces to the VDD and GND.

    5. Fig: Adding the VDD and GND.

  5. The testbench is complete.

Simulating the Schematic

  1. Enter simulation mode by clicking the ‘Enter Simulation Mode’ icon in the Schematic Edit Palette.
  2. Click on the New Configuration button and choose Digital Simulation.
  3. Click on the Setup Sim Session icon, the first icon, on the left panel, and then on Simulator/Viewer button. Choose your simulator as Eldo and Viewer as EZwave in the pop up window.
  4. Click again on the Setup Sim Session icon, the first icon, on the left panel, and then choose 'Environment...' this time. A window should pop up. Choose 'Run Simulation and Display Waveforms' in the Auto-Run Simulation Setup section. Click OK.
  5. Then click on the Setup Analysis icon (third one from the top) to choose the type of analysis. Check the Transient analysis checkbox.
  6. Add the inputs, select an input net, say A, and click on the fifth icon, Setup Forces/ICS icon, on the left panel and choose Add. Select Pulse as the type of source and set the Pulse Value to be 5, Pulse Width to be 50e-9 and Period to be 100e-9.

    7. Fig: Setting up the Pulse input.

  7. Add a Pattern source to the other input net and set the High Value to 5, Low to 0, Delay to 0, Rise and Fall Time to 1e-9, Pattern duration to 10e-9 and the Pattern to 1100110101.
  8. Add a DC source of Value 5 to the net connecting VDD and a DC source of Value 0 to the net connecting GND.
  9. Setup the Library to ami05.mod by clicking on the Setup Lib/Temp/Inc icon, the second icon, and then on Libraries. Set the library path to /usr/local/mentor/adk/technology/ic/models/ami05.mod either by typing it or browsing through it.

    10. Fig: Setting the Library Paths

  10. Ctrl-click to select all the nets, then click on the Wave Outputs icon in the left panel. It is the ninth icon from the top. Then click on 'Save Selected'.
  11. Choose to Save the Voltage, uncheck the Plot item(s) checkbox on the popup window, and click OK.
  12. To create an input netlist click on the Netlist icon (thirteenth icon from the top) in the left panel. A status window should open and read ‘Done…’
  13. Start the simulator by clicking on the Run Simulation button (fourteenth icon from the top). This should bring up the EZwave window. Browse through the graphs to view the result of the simulation.

Fig: Simulation of a transistor level NOR gate.