E77 Fall 2007

MWF 9:30-10:20, Hicks 303

Instructor:
Tali Moreshet
Hicks 218, x8331

Office Hours:
TBD, Open door policy

Course Description:

This course is an introduction to the design, analysis, and modeling of digital integrated circuits, with an emphasis on hands-on chip design using CAD tools. We will focus on CMOS technology, and cover both full custom layout design and synthesis using Verilog.

syllabus

Textbook:

Neil H.E. Weste and David Harris, CMOS VLSI Design, A Circuits and Systems Perspective, third edition, Addison Wesley, 2005.

Links:

Tentative Class Schedule

NOTE: The links on this page are not accessible from outside Swarthmore.

Week	Day	Topics	Readings	Labs & HW
1	Sep 3	Introduction Review of digital logic	Chapter 1	Lab 1: Gate-level design
	Sep 5
	Sep 7
2	Sep 10	Review of digital logic Introduction to VLSI design	Chapter 1	Homework 1
	Sep 12
	Sep 14
3	Sep 17	Designing a System-on-Chip Spice MOS transistor theory	Chapter 5 Chapter 2	Lab 2: Transistor-level design
	Sep 19
	Sep 21
4	Sep 24	MOS transistor theory -cont Layout (slides)	Chapter 3	Homework 2
	Sep 26
	Sep 28
5	Oct 1	Delay estimation Logical effort	Chapter 4	Lab 3: Intro to Layout
	Oct 3
	Oct 5
6	Oct 8	Logical effort - cont Logic families Dynamic logic	Chapter 6	Homework 3
	Oct 10
	Oct 12
Fall Break
7	Oct 22	Dynamic logic - cont Introduction to Verilog	Chapter 6 Appendix A	Lab 4: Dynamic logic + Intro to Verilog
	Oct 24
	Oct 26
8	Oct 28	Sequential logic - latches & FFs FSM design in Verilog	Chapter 7	Homework 4
	Oct 31
	Nov 2
9	Nov 5	sequential logic - timing EXAM - Nov. 8, 7pm	Chapter 7	Lab 5: Final layout
	Nov 7
	Nov 9
10	Nov 12	Interconnect Power dissipation	Chapter 4	Homework 5
	Nov 14
	Nov 16
11	Nov 19	Memory SRAM Thanksgiving	Chapter 11	Final project
	Nov 21
	Nov 23
12	Nov 26	DRAM, ROM, CAM PLAs, FPGAs Synthesis design flow	Chapter 11 Chapter 8
	Nov 28
	Nov 30
13	Dec 4	Testing Final project presentations	Chapter 9
	Dec 6
	Dec 8
	Dec 10

E77: VLSI Design Fall 2007

E77: VLSI Design
Fall 2007