E25:  Principles of Computer Architecture
Spring 2013

M W F 11:30-12:20, Hicks 211

Instructor:
Tali Moreshet
Hicks 218, x8331


Office Hours:
Tues. 2-4pm, open door policy


Course Description:

This course is an introduction to computer architecture. In this class, we will focus on microprocessor design, including CPU and memory, the interface between hardware and software, and an introduction to multiprocessors. The labs for this course will focus on microprocessor characteristics and design, using Verilog, a hardware description language, and performance simulators.  A course project enables the students to explore a particular topic of their choice in depth.

syllabus



Textbooks:

Links:


Tentative Class Schedule

NOTE: Some of the links on this page are not accessible from outside Swarthmore.

Week Dates Topics Readings & Handouts Labs & HW
1 Jan 21-Jan 25
  • Introduction
  • Computer history
  • Measuring performance
  • (Verilog review)
Chapter 1
Slides
Slides
(See Verilog links above)
Lab 1
Quartus II Abbreviated Manual
2 Jan 28-Feb 1
  • Performance, power and technology trends
  • ALU Arithmetic
  • Floating point number representation
  • (Digital systems review)

Chapter 1
Slides
Chapter 3.1-3.5
Slides
(Chapter 2.4, Appendix C.1-C.3, C.5-6)

Homework 1

3 Feb 4-Feb 8
  • Instruction Set
  • MIPS assembly
Chapter 2.1-2.7
Slides
MIPS Green Card
Slides
Lab 2
Example MIPS program
Download SPIM from here
4 Feb 11-Feb 15
  • Addressing Modes
  • Datapath and control
Chapter 2.10, 2.11, 2.16, 2.17
Appendix B
Chapter 4.1-4.4
Slides
Chapter 4.4-4.6
Slides
(Appendix D)
Homework 2
5 Feb 18-Feb 22
  • Pipelining
  • Hazards, forwarding
Chapter 4.4-4.6
Slides
Slides
Slides
Homework 3

6 Feb 25-March 1
  • EXAM : Wed. 2/27, in class
  • Hazards, forwarding - cont
Chapter 4.6, 4.5, 4.7-4.9
Lab 3
( register_file.v)
7 March 4-March 8
  • Exceptions
  • Branch prediction
Chapter 4.6, 4.5, 4.7-4.9
Slides
BPred Handouts
Homework 4
Spring Break
8 March 18-March 22
  • Caching
  • Memory
Chapter 5.1-5.3, 5.5
Slides
Slides
Homework 5
9 March 25-March 29
  • SimpleScalar
  • Virtual Memory
Chapter 5.4
Slides
Lab 4
www.SimpleScalar.com
10 April 1-April 5
  • Virtual Memory - cont
  • Exploiting ILP
  • Scheduling
Chapter 4.10
Slides
Homework 6

Final Project
11 April 8-April 12
  • Scheduling - cont
  • Cache coherence
  • Multiprocessors
Tomasulo Handouts
Slides
Chapter 7.1-7.6, 2.11, 5.8
Slides
Homework 7

Research Paper Prep
12 April 15-April 19
  • Intel Pentium 4
  • Intel Core Duo
  • AMD Opteron, Barcelona
Intel Pentium 4
Intel Core Duo
Slides
AMD Opteron: Sections 2.17, 3.7, 4.11, 5.10
Research Paper Prep
13 April 22-April 26
  • AMD "Magny Cours" Memory Hierarchy
  • GPUs
AMD Opteron Memory Hierarchy
GPUs: Section 7.7, Appendix A, (Fermi GF100 GPU Architecture)
Research Paper Prep
14 April 29-May 3
    Final project presentations
  • Mon: Jackie & Kitty - Fast ALU
    Callen & Daniel - Fast Multiply & Divide
    Jordan & Sam - Fast Multiply & Divide
  • Wed: Gautam - Pipelined MIPS
    David & Greg - Pipelined MIPS w/ hazard detection, forwarding, and bpred
    Noah & Davis - Static dual issue MIPS
    Caleb - Pipelined MIPs
  • Fri: Peter - MIPS single-cycle with caching
    Chris - Evaluation of memory hierarchies
    Rachel - Victim caches
    Elliot & Peng - Pseudo and adaptive LRU/LFU schemes
   
Final Exam: 5/10 9am