E25:  Principles of Computer Architecture
Spring 2012

T Th 8:30-9:45, Hicks 303

Instructor:
Tali Moreshet
Hicks 218, x8331


Office Hours:
Wed. 1-3pm, open door policy


Course Description:

This course is an introduction to computer architecture. In this class, we will focus on microprocessor design, including CPU and memory, the interface between hardware and software, and an introduction to multiprocessors. The labs for this course will focus on microprocessor characteristics and design, using Verilog, a hardware description language, and performance simulators.  A course project enables the students to explore a particular topic of their choice in depth.

syllabus



Textbooks:

Links:


Tentative Class Schedule

NOTE: Some of the links on this page are not accessible from outside Swarthmore.

(Appendix D)
(Appendix D)
Week Dates Topics Readings & Handouts Labs & HW
1 Jan 16-Jan 20
  • Introduction
  • Computer history
  • Measuring performance
Chapter 1
Slides
 
2 Jan 23-Jan 27
  • Performance, power and technology trends
  • ALU Arithmetic
  • (Digital systems review)
  • Floating point number representation

Chapter 1
Slides
Chapter 3.1-3.5
Slides
(Chapter 2.4, Appendix C.1-C.3, C.5-6)
Slides

Homework 1

Lab 1
ALU.do
ModelSim tutorial (see step 5)
Erik Cheever's .do file reference
3 Jan 30-Feb3
  • (Verilog review)
  • Instruction Set
  • MIPS assembly
See Verilog links above
Chapter 2.1-2.7
Slides
 
4 Feb 6-Feb 10
  • MIPS assembly - cont
  • Addressing Modes
  • Datapath and control
Chapter 2.10, 2.11, 2.16, 2.17
Appendix B
Chapter 4.1-4.4
Slides
Homework 2

Lab 2
Example MIPS program
Download SPIM from here
5 Feb 13-Feb 17
  • Datapath and control - cont
  • Pipelining
Chapter 4.4-4.6
Slides
Homework 3
Lab 3
( register_file.v)
6 Feb 20-Feb 24
  • EXAM : Tues. 2/21, in class
  • Pipelining - cont
  • Hazards, forwarding
Chapter 4.6, 4.5, 4.7-4.9
Slides
 
7 Feb 27-March 2
  • Hazards, forwarding - cont
  • Exceptions
  • Branch prediction
Chapter 4.6, 4.5, 4.7-4.9
Slides
BPred Handouts
Slides
Homework 4
Spring Break
8 March 12-March 16
  • Caching
  • Memory
Chapter 5.1-5.3, 5.5
Slides
Homework 5
9 March 19-March 23
  • SimpleScalar
  • Virtual Memory
Chapter 5.4
Slides
Lab 4
www.SimpleScalar.com
10 March 26-March 30
  • Exploiting ILP
  • Scheduling
  • Advanced ILP techniques
  • Becca: XMT
Chapter 4.10
Slides
XMT_Slides
Lab 5
task1_serial_template.c
Input files
XMT limitation summary
The XMT Webpage
11 April 2-April 6
  • Scheduling - cont
  • Cache coherence
  • Multiprocessors
  • Multithreading
  • Synchronization
Tomasulo Handouts
Slides
Chapter 7.1-7.6, 2.11, 5.8
Final Project

Homework 6

Research Paper Prep
12 April 9-April 13
  • Intel Pentium 4 (Steven & Jordan)
  • Intel Core Duo (David)
  • AMD Opteron, Barcelona (Abel)
  • AMD "Magny Cours" Cache Hierarchy (Eliza & Danielle)
Intel Pentium 4
Intel Core Duo
AMD Opteron: Sections 2.17, 3.7, 4.11, 5.10
AMD Opteron Cache Hierarchy
 
13 April 16-April 20
  • IBM Power7 (Ben)
  • Cell (Becca)
  • GPUs (Kyle & Wesley)
  • Sun Niagara (April & Katie)
  • ARM (Chris)
Energy Management in Power7
The Cell Processor
GPUs: Appendix A
SPARC T4 (formerly Niagara)
Parallelism and the ARM ISA
 
14 April 23-April 27
  • Final project presentations
  • Tues: Becca, Katie & April, David & Ben, Abel & Chris
  • Thur: Steven & Jordan, Eliza & Danielle, Wesley & Kyle
   
Final Exam: 05/03, 9am, Hicks 211