Courses
E08 How Do Computers Work?
E15 Fundamentals of Digital Systems
E24 VLSI Design
E25 Principles of Computer Architecture
E12 Physical Systems Analysis - Labs
Research Interests
Computer
architecture.
Energy-efficiency in
shared memory multiprocessor and many-core systems, transactional memory and embedded systems.
Academic History
Selected Publications
- Tali Moreshet, Uzi Vishkin, and Fuat Keceli, "Parallel Simulation of Many-core Processors: Integration of Research and Education", ASEE Annual Conference, June 2012.
- Fuat Keceli, Tali Moreshet, and Uzi Vishkin, "Power-Performance Comparison of Single-Task Driven Many-Cores", International Conference on Parallel and Distributed Systems (ICPADS 2011), December 2011.
- Cesare Ferri, Andrea Marongiu, Benjamin Lipton, Tali Moreshet, R. Iris Bahar, Luca Benini and Maurice Herlihy, "SoC-TM: Integrated HW/SW Support for Transactional Memory Programming on Embedded MPSoCs", International Conference on Hardware/Software Codesign and System Synthesis, October 2011.
- Fuat Keceli, Tali Moreshet and Uzi Vishkin, "Thermal Management of a Many-Core Processor under Fine-Grained Parallelism", Euro-Par Workshop on Highly Parallel Processing on a Chip (HPPC 2011), August 2011, in conjunction with Euro-Par 2011.
- Cesare Ferri, Samantha Wood, Tali Moreshet, R. Iris Bahar and Maurice Herlihy, "Embedded-TM: Energy and complexity-effective hardware transactional memory for embedded multicore systems", Journal of Parallel and Distributed Computing, vol. 70, no. 10, pp. 1042-1052, October 2010.
- Cesare Ferri, Samantha Wood, Tali Moreshet, R. Iris Bahar and Maurice Herlihy, "Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems", International Conference on High-Performance Embedded Architectures and Compilers, January 2010.
- Fuat Keceli, Tali Moreshet and Uzi Vishkin, "Power Study of a 1000-Core Processor", International Workshop on Logic and Synthesis, June 2008.
- Cesare Ferri, R. Iris Bahar, Tali Moreshet, Amber Viescas and Maurice Herlihy, "Energy Efficient Synchronization Techniques for Embedded Architectures", ACM Great Lakes Symposium on VLSI, May 2008.
- Cesare Ferri, Amber Viesdcas, Tali Moreshet, R. Iris Bahar and Maurice Herlihy, "Energy Implications of Transactional Memory for Embedded Architectures", Workshop on Exploiting Transactional Memory and Other Hardware-Assisted methods, April 2008.
- Cesare Ferri, Tali Moreshet, R. Iris Bahar, Luca Benini and Maurice Herlihy, "A Hardware/Software Framework for Supporting Transactional Memory in a MPSoC Environment", ACM SIGARCH Computer Architecture News, Vol. 35, No.1, March 2007.
- Tali Moreshet, R. Iris Bahar and Maurice Herlihy, "Energy-Aware
Microprocessor Synchronization: Transactional Memory vs. Locks",
Workshop on Memory Performance Issues, held in conjunction
with the International Symposium on High-Performance Computer
Architecture, Austin, TX, February 2006.
- Tali Moreshet,
R. Iris Bahar and Maurice Herlihy, "Energy
Reduction in Multiprocessor Systems Using Transactional Memory",
International Symposium on Low Power Electronics and Design,
San Diego, CA, August 2005.
- Tali Moreshet
and R. Iris Bahar, "Effects
of Speculation on
Performance
and Issue Queue Design", IEEE Transactions on VLSI Systems, October
2004.
- Tali Moreshet
and R. Iris Bahar, "Power-Aware
Issue Queue Design
for
Speculative Instructions", Design Automation Conference, Anaheim,
CA,
June 2003.
- Tali Moreshet
and R. Iris Bahar, "Power-Aware Issue Queue Design
for
Speculative Instructions", Workshop on Logic and Synthesis, Laguna
Beach, CA, May 2003.
- Tali Moreshet,
"Considering the Effect of Load Hit Speculation on
Processor Performance and Issue Queue Design", Master of Science
Thesis, May 2003.
- Tali
Moreshet and R. Iris Bahar, "Complexity-Effective
Issue
Queue
Design Under Load-Hit Speculation", Workshop on
Complexity-Effective
Design, held in conjunction with the International Symposium on
Computer Architecture, Anchorage, AK, May 2002
