Courses

E15/CS38 Fundamentals of Digital Systems

E24 VLSI Design

E25/CS25 Principles of Computer Architecture

E12 Physical Systems Analysis - Labs                                

Academic History

• Ph.D in Electrical Engineering, concentration in Computer Engineering
  Brown University
  Dissertation: Power and Energy-Aware Architectural Techniques for High-Performance Uniprocessor and Multiprocessor Systems
  Advisors: R. Iris Bahar, Maurice Herlihy
  
  
• M.Sc. in Electrical Engineering, concentration in Computer Engineering
  Brown University
  Thesis: Considering the Effect of Load Hit Speculation on Processor Performance and Issue Queue Design
  Advisor: R. Iris Bahar
  
  
• B.Sc. in Computer Science
  Technion, Israel Institute of Technology
  

• Cesare Ferri, Samantha Wood, Tali Moreshet, R. Iris Bahar and Maurice Herlihy, "Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems", International Conference on High-Performance Embedded Architectures and Compilers, January 2010.
  
  
• Fuat Keceli, Tali Moreshet and Uzi Vishkin, "Power Study of a 1000-Core Processor", International Workshop on Logic and Synthesis, June 2008.
  
  
• Cesare Ferri, R. Iris Bahar, Tali Moreshet, Amber Viescas and Maurice Herlihy, "Energy Efficient Synchronization Techniques for Embedded Architectures", ACM Great Lakes Symposium on VLSI, May 2008.
  
  
• Cesare Ferri, Amber Viesdcas, Tali Moreshet, R. Iris Bahar and Maurice Herlihy, "Energy Implications of Transactional Memory for Embedded Architectures", Workshop on Exploiting Transactional Memory and Other Hardware-Assisted methods, April 2008.


• Cesare Ferri, Tali Moreshet, R. Iris Bahar, Luca Benini and Maurice Herlihy, "A Hardware/Software Framework for Supporting Transactional Memory in a MPSoC Environment", ACM SIGARCH Computer Architecture News, Vol. 35, No.1, March 2007.
  
  
• Tali Moreshet, R. Iris Bahar and Maurice Herlihy, "Energy-Aware Microprocessor Synchronization: Transactional Memory vs. Locks", Workshop on Memory Performance Issues, held in conjunction with the International Symposium on High-Performance Computer Architecture, Austin, TX, February 2006.
  
  
• Tali Moreshet, R. Iris Bahar and Maurice Herlihy, "Energy Reduction in Multiprocessor Systems Using Transactional Memory", International Symposium on Low Power Electronics and Design, San Diego, CA, August 2005.
  
  
• Tali Moreshet and R. Iris Bahar, "Effects of Speculation on Performance and Issue Queue Design", IEEE Transactions on VLSI Systems, October 2004.
  
  
• Tali Moreshet and R. Iris Bahar, "Power-Aware Issue Queue Design for Speculative Instructions", Design Automation Conference, Anaheim, CA, June 2003.
  
  
• Tali Moreshet and R. Iris Bahar, "Power-Aware Issue Queue Design for Speculative Instructions", Workshop on Logic and Synthesis, Laguna Beach, CA, May 2003.
  
  
• Tali Moreshet, "Considering the Effect of Load Hit Speculation on Processor Performance and Issue Queue Design", Master of Science Thesis, May 2003.
  
  
• Tali Moreshet and R. Iris Bahar, "Complexity-Effective Issue Queue Design Under Load-Hit Speculation", Workshop on Complexity-Effective Design, held in conjunction with the International Symposium on Computer Architecture, Anchorage, AK, May 2002