module DetectThreeOnes(clk, rst, x, y);

	input clk, rst, x;
	output y;
	
	reg [1:0] state;
	
	always @(posedge clk or negedge rst)
	begin
		if (~rst)
			state <= 2'b00;
		else
			case (state)
				2'b00: state <= (x ? 2'b01 : 2'b00);
				2'b01: state <= (x ? 2'b10 : 2'b00);
				default: state <= (x ? 2'b11 : 2'b00);
			endcase
	end
		
	assign y = (state[0] & state[1]);
	
endmodule