ModelSim Altera Starter Edition

Downloading and installing the software

The software is already installed on the PC's in Hicks 213.

If you want to run it on your home computer, you can download it for Windows from Altera's web site.

Starting a new project

From the Start menu, choose Altera -> ModelSim-Altera -> ModelSim-Altera to start the program. After a brief pause, you should see the application window.

Do File -> New -> Project...

Make the Project Name be homework5, and the Project Location be K:\verilog\homework5. Do not change the Default Library Name or the Copy Settings From boxes. If it asks if you want to create the directory, click Yes.

Adding files

After the project is created, you will get a window saying "Add items to the Project". Choose "Create New File". For File Name, enter simple.v, and for Add file as type, choose Verilog. Click OK, and then click Close on the Add items window.

In the Project window, you will see the empty file simple.v with a question mark next to it. Double-click the simple.v filename to bring up an editor window, and paste in these contents:

simple.v:

module simple(A, B);

   input  [3:0] A;
   output [3:0] B;

   // mix up the input bits
   assign B = { A[0], A[2], A[1], A[3] };

endmodule

Right-click in the Project window, and choose Add to Project -> New File... For File Name, enter simple_tb.v, and for Add file as type, choose Verilog again. Click OK.

Double-click on simple_tb.v in the Project window to edit the file, and paste in these contents:

simple_tb.v:

module simple_tb;

   reg [3:0] A = 4'b1010;

   wire [3:0] B;

   initial
     begin
        $monitor("A is %b, B is %b.", A, B);
        #50 A = 4'b1100;
        #50 $stop;
     end

   simple s(A, B);

endmodule

Compiling your Verilog program

You need to compile your Verilog program before you can simulate it. From the Compile menu, choose Compile All. You should see output in the bottom window to the effect of

# Compile of simple.v was successful.
# Compile of simple_tb.v was successful.
# 2 compiles, 0 failed with no errors.

Running the simulation

From the Simulate menu, choose Start Simulation...

A Start Simulation window will appear. The first entry in the window should be a Library called "work". Expand it, and select both Verilog source files (simple.v and simple_tb.v) by holding down Shift while clicking, then click OK.

Your workspace should now have a "sim" window in it, with several items. Right click on the simple_tb item, and choose Add -> To Wave -> All items in region and below. A Wave window will appear, ready to plot your data.

From the Simulate menu, choose Run -> Run -All.

You should see the following output in the bottom of the window:

# A is 1010, B is 0011.
# A is 1100, B is 0101.
# Break in Module simple_tb at K:/verilog/homework5/simple_tb.v line 13

If you switch back to the Wave window, you will see your data plotted.



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