This lab meets in Hicks 310 (other labs will be in Hicks 213)
In this lab you will use a breadboard and MSI/SSI (Medium/Small Scale Integration) TTL (Transistor Transistor Logic) Integrated Circuits to design a simple circuit. SSI circuits generally have on the order of one hundred transistors, MSI on the order of one thousand.
Notes regarding part numbers for MSI/SSI gates: The chips you will be using start with the two numbers 74 followed by two (or perhaps 3) numbers. The second set of numbers specifies the function of the device. Between the 74 and the other numbers are some letters which specify the technology used. For example a 7432 holds 4 two input or gates. A 74L32 has the same configuration of gates, but is low power; 74H32 is high speed; 74S32 is Schottky clamped (don't worry about what this does, suffice it to say it makes the device faster); 74LS32 is low power and Schottky clamped; 74ALS32 is advanced low power Schottky clamped. The devices you will use will probably all be LS typed devices; if you can't find an LS part, feel free to substitute any other type.
Some useful 74xx chips (don't use a part if it says it is "open collector" - e.g., the 7406 open collector invertor).
| Device | Function |
| 7400 | Quad Two input nand |
| 7402 | Quad Two input nor |
| 7404 | Hex invertor |
| 7408 | Quad Two input nand |
| 7410 | Triple Three input nand |
| 7411 | Triple Three input and |
| 7420 | Dual Four input nand |
| 7432 | Quad Two input or |
| 7486 | Quad Two input xor |
| 7493 | 4 bit binary counter |
Set up a counter (74LS93) to count from 0 to 5 and then reset when it gets to 6. Figure out how to do this using the data sheet. Don't forget to hook up power (i.e, Vcc=5 volts) and ground to the chip. If you can't figure out the data sheet in about 30 minutes, come talk to me and we'll work it out. Hook up the outputs of the counter to three LED indicators on the breadboard to demonstrate that this works.
Put a TTL compatible clock signal (from the breadboard) into one input of an and or nand gate, and connect the other to a switch that is either 5 volts or zero. This allows you to control the clock. Connect the output of the gate to the clock input of the counter. Verify that you can control the operation of the counter with the switch.
Arrange seven LED's on the breadboard as shown below.
Use Karnaugh maps to design a circuit that lights up the LED's as shown (the input to the circuit should be the output of the counter):
|
Count |
0 |
1 |
2 |
3 |
4 |
5 |
|
LED's lit |
|
|
|
|
|
|
Some practical concerns:
To light an LED the outputs should be
active low (that is, the LED will light up when the output of the gate
connected to it is low). This is because TTL can
sink (current goes in to gate) that it can source (current goes out of
gate). A typical connection is shown below
Make sure you consider this when making your Karnaugh Diagrams.
LED's are found in the cabinets in Hicks 310.
The cathode (lower part) of the LED has a small, flat spot on the case of the LED.
Make sure you connect power and ground to each of your chips.
LED's a and g (also c/e, b/f) are always on together, so you can put the two LED's in series. You will need to decrease the resistor to keep the current the same as in the single LED -- brightness is related to current.
Set the speed of your TTL clock to be very fast. Each time you push the button you should get a random roll of the die. Take 36 rolls and show that the results are random.
When you are finished, demonstrate your circuit to me.
Do a design that uses minimal logic chips (this may be different than the minimal SOP result).
In the diagrams above I used the lights a and g for both count 1 and count 2 (numbers 2 and 3 on the die), but you could use a and g for one of them and b and f for the other. Can this reduce logic?
If you are simply trying to get a random roll, the order of the outputs can be rearranged (the die need not count from 1 to 6 sequentially). Can this reduce the logic used?
Can you simplify the circuit based on the fact that you have multiple outputs?
What is the minimal circuit (i.e., minimal cost) you can come up with using the techniques described?
Completed Karnaugh maps of the described task.
A schematic diagram of your completed circuit (including counter...). This should show the gates and how they are connected, not a pin out of the chips. You can use a block diagram for the counter (showing clock input, resets and outputs).
Verification that your circuit works.
A Quartus demonstration that the circuit works. There is a Quartus tutorial in the back of your book; use the schematic entry method described in Appendix B.1 through B.3. Don't use VHDL for this lab.
Use Karnaugh maps to design a loaded die
(i.e, one with unequal probablities). The numbers 2, 3, 4, 5, and 6
should appear 5 out of 32 throws, but the number 1 should appear 7 out of 32
throws. You don't need to build the design, but give your minimum
sum-of-products equations.
Anything associated with the extras (or anything else you did).
