E15 Laboratory 5

Verilog State Machines

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This week's lab is fairly short so you can begin thinking about, and planning for, the end-of-semester project.   Project Guidelines and Deadlines.

Task 1:

Download and run the code in E15Lab5Task1.v (your top level entity), E15Lab5Clock1Hz.v, and LongSR.v (shown below).  It implements a maximal length sequence shift register and displays it on green LED's while the output of the register (X, also the leftmost bit of the SR) is  shown on a red LED.

E15Lab5Task1.v

E15Lab5Clock1Hz.v

LongSR.v

Draw a state machine that has as input a sequence of bits, and detects when there have been three high bits in a row. 

Write code that detects when X has been high for three counts in a row and then lights a red LED. 

Use the following guidelines for your code.

• Make sure your code has only the allowable warnings (or that you have discussed other warnings with me).  I would like a list of your warnings as part of your writeup.
• Make sure all states change on the rising edge of the 27 MHz clock.
• Split your code into two sections, one (sequential) section that implements the sequencing of the state machine, and one (combinational) section that determines outputs based upon the state.

Task 2

Draw a state machine to represent a stop-light that has two lights, NS, and EW.  There are 16 states, and the progression goes as follows:

• State 0-5: NS Red, EW Green.  Once in state 5, remain in that state until a car appears on the NS road (noted by KEY[0] being pushed), at which time the state progresses to state 6.
• State 6-7: NS Red, EW Yellow.
• State 8: NS Red, EW Red.
• State 9-12: NS Green, EW Red.
• State 13-14: NS Yellow, EW Red.
• State 15: NS Red, EW Red.

Implement the state machine in Verilog using the same guidelines as for Task 1. 

Task 3

Something more advanced - on the order of the game from lab 2, or writing to the LCD.  Show the state diagram and implement the state machine in Verilog using the same guidelines as for Task 1. 

To Turn in:

The grading of each subtask is as follows.

• Task 1
  • State Diagram (15 pts - Basic)  Neat and complete.
  • (40 pts - Basic)  Neatly indented and thoroughly commented Verilog code.  By "thoroughly commented" I mean that the comments should be sufficient that somebody with Verilog experience (but who is not in the class) could understand completely what you did (check LongSR.v for an example).  You may include a separate document (so you can include schematics...) if you would like to do so.
  • (5 pts - Basic) - Include a listing of all of the warnings you received when compiling, fitting....
  • Demo to me.
• Task 2
  • State Diagram (10 pts - Basic)  Neat and complete.
  • (25 pts - Basic)  Neatly indented and thoroughly commented Verilog code.
  • (5 pts - Basic) - Include a listing of all of the warnings you received when compiling, fitting....
• Task 3:
  • (15 pts - Advanced)  Neat and complete documentation (including a list of warnings).  Also demo to me.

← Back to E15 Lab page ←

Please contact me if you find any errors or other problems (e.g., something is unclearly stated) in this web page