E15 Laboratory 4
Verilog State Machines

Task 1:

Remember to put your Quartus projects in a folder on the desktop (or other location of your choosing, but don't use the default location).

Download and run the code in E15Lab4Task1.v (your top level entity), E15Lab4Clock1Hz.v, and LongSR.v (shown below). E15Lab4Task1.v implements a maximal length sequence shift register and displays it on green LED's while the output of the register (X, also the leftmost bit of the SR) is  shown on a red LED.   You also need to include the E15DE2_IO.qsf file and import the assignments.

E15Lab4Task1.v

E15Lab4Clock1Hz.v

LongSR.v

Draw a state diagram that has as input a sequence of individual bits, and detects when there have been three high (or more) bits in a row. 

Write code (in a module called E15Detect3.v; see E15Lab4Task1.v for input list to module) that detects when X has been high for three counts in a row and then lights a red LED. 

Use the following guidelines for your code.

The state machine you will build will be slightly different from the ones we did in class.  For the sequential part of the machine instead of

always @(posedge Clock)   
 // ... your code
end

You will use

always @(posedge Clock)   
if (En1Hz)                  
begin
 // ... your code
end

where "En1Hz" is a signal that is only high for one cycle per second.  This has the effect of slowing transitions of the state machine to once per second, so that you can observe in real time.  Otherwise the code should be as discussed in class.

Once you get your design working (or if you are having difficulties) simulate the design.  Simulating the exact design as is would be extremely slow since 50,000,000 clock pulses must be generated before the shift.  To fix that, change the instantiation of the shift register and your module to:

LongSR mySR(CLOCK_50, 1'b1, LEDG, X);
E15Detect3 mySeqDet(CLOCK_50, 1'b1, X, Y); 

This causes the shift register to be active on each positive edge of the clock.  Remember that to do a simulation you'll need to remove the pin associations (Assignment→Remove Assignments and select "Pin, Location and Routing Assignments".   Remember to reimport the assignments before you reprogram the board.  Simulate at least 100 cycles of the clock.

Task 2

 Remember to reimport the assignments before you reprogram the board after any simulation.

Draw a state diagram to represent a stop-light that has two lights, NS, and EW.  There are 16 states, and the progression goes as follows:

Implement the state machine in Verilog using the same guidelines as for Task 1.

Task 3

Repeat Task 1 with a Mealy state machine (the combinational section determines the output based upon the current state as well as the input.  Remember to reimport the assignments before you reprogram the board after any simulation.  A Mealy machine often has fewer states than a Moore machine, and the output often arrives sooner.

Task 4

Optional:  Something more advanced - on the order of the game from lab 2, or the traffic light with only 6 states (with a counter).  Show the state diagram and implement the state machine in Verilog using the same guidelines as for Task 1. 


To Turn in (as a pdf on moodle):


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