E15 Laboratory 3

Combinational Logic in Verilog

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Useful references for E15 labs

You might want to print out the Synthesizable Verilog Quick Reference (pdf) 
(orignally at http://www.cl.cam.ac.uk/teaching/0910/ECAD+Arch/files/verilogcheatsheet.pdf)

In this lab you will be performing many of the same tasks that you did in the last two labs, but also going beyond (as you learn more complex methods).  The goal is to teach you new methods, but also to give you an appreciation of various solutions to the same problem.

Task 0: Quartus for Verilog tutorial

Go through the tutorial describing the writing, compiling, simulating and running of Verilog code using Quartus and the DE2 board.

Task 1: Simulating a traffic light.

The goal is to design a stoplight for which the signals should change according to the following table:

Don't use any sequential logic - just use combinational logic.  This means no incrementing variables...  The only sequential logic you need are the two verilog files "E15Clock1Hz.v" and "E15Counter.v"

Task 1a: Using the files E15Clock1Hz.v and E15Counter.v, write Verilog code to implement the stop light using "Gate-Level Modeling" (described on page 159 of your text) so that it is immediately apparent from your code what the resulting circuit would look like.

Task 1b: Using your code, simulate your circuit, but remove the the clock and counter.

Task 1c: Repeat 1a using "Dataflow Modeling" (page 165).

Task 2: Working with 7 segment displays.

Don't use any sequential logic - just use combinational logic.  This means no incrementing variables...  The only sequential logic you need are the two verilog files "E15Clock1Hz.v" and "E15Counter.v"

Task 2a: Write code that counts from 0 to 9 on Hex0 (the rightmost seven segment display).  Two things:

1. The LED's are common anode (i.e., they are active low; they light when the LED segment gets a logic 0)
2. The LED segments are defined in E15DE2_IO.qsf, and described in DE2_Pin_Table.pdf.

Task 2b: Write code that counts from 00 to 99 on the seven-segment displays Hex1-Hex0.   You should include a separate module that converts from BCD to 7 segment that is used twice (don't just double the length of your code).

 You'll have to think a while:  how can you get a counter that goes up to 99?  You shouldn't change any of the code I gave you.  See me if you can't figure out how to do it after about 10-15 minutes.

Task 2c: (Advanced) Adapt your code so the leftmost number is not displayed if it is a zero.  There are many ways to handle the blanking - an easy one is to include another input to the module that determines if it should display zero, or be blank.

Task 3 (Advanced): Die.

Write code to implement the Die from the first two labs.  The display should blank when Key[0] is pushed, and yield a random number when Key[0] is released.

Task 4 (Advanced): Count on me.

Task 4a: Generate addition tables. 
Have the digits Hex6 and Hex4 count from 0 to 9 (Hex 4 should count 10 times faster than Hex6 so you get all 100 possible combinations).  Add the two numbers, and have the result appear in Hex3 and Hex2.  As part of your solution write a module "BCD_HalfAdd" that has as inputs two BCD numbers, and has as output one BCD number and a "carry" bit to signify the result was greater than 10.

Task 4b: Make addition flash cards. 
Repeat the previous task with two 2-digit hex numbers (in Hex7-Hex6 and Hex5-Hex4).  Make sure you get all 10,000 possible solutions.  The sum should appear in Hex3-Hex2-Hex1.  Set the numbers to increment at 50 MHz, and push KEY[0] to stop the counters and display the result.

To Turn in:

The grading of each subtask is as follows.

• Task 1
  • Task 1a:  (20 pts - Basic)  Neatly indented and thoroughly commented Verilog code.  By "thoroughly commented" I mean that the comments should be sufficient that somebody with Verilog experience (but who is not in the class) could understand completely what you did.
  • Task 1b:  (20 pts - Basic)  Thorough and neatly presented results.
  • Task 1c:  (20 pts - Basic)  Neatly indented and thoroughly commented Verilog code.  Demo to me.
• Task 2
  • Task 2a:  (20 pts - Basic)  Neatly indented and thoroughly commented Verilog code. 
  • Task 2b:  (20 pts - Basic)  Neatly indented and thoroughly commented Verilog code.   Demo to me.
  • Task 2c:  (5 pts - Advanced)  Neatly indented and thoroughly commented Verilog code.
• Task 3: (5 pts - Advanced) Neatly indented and thoroughly commented Verilog code.
• Task 4
  • Task 4a: (10 pts - Advanced) Neatly indented and thoroughly commented Verilog code. Demo to me.
  • Task 4b: (10 pts - Advanced) Neatly indented and thoroughly commented Verilog code.  Demo to me.

← Back to E15 Lab page ←

Please contact me if you find any errors or other problems (e.g., something is unclearly stated) in this web page