# E15 Laboratory 3

## Combinational Logic in Verilog

Useful references for E15 labs

You might want to print out the Synthesizable Verilog Quick Reference (pdf

In this lab you will be performing many of the same tasks that you did in the last two labs, but also going beyond (as you learn more complex methods).  The goal is to teach you new methods, but also to give you an appreciation of various solutions to the same problem.

### Task 0: Quartus for Verilog tutorial

Go through the tutorial describing the writing, compiling, simulating and running of Verilog code using Quartus and the DE2 board.

### Task 1: Working with 7 segment displays.

Don't use any sequential logic - just use combinational logic.  This means no incrementing variables...  The only sequential logic you is the verilog file E15Counter1HzB.v

Simulate the code to verify that it works as expected.

Task 1a: Write a module called BIN2SEVENSEG that acts as a binary to 7 segment decoder.  It takes as input a four bit binary number, and for output lights a seven segment LED on HEX0.
f

Two things you need to know:

1. The LED's are common anode (i.e., they are active low; they light when the LED segment gets a logic 0)
2. The LED segments are defined in E15DE2_IO.qsf, and described in DE2_Pin_Table.pdf (for the latter you need to refer to information on page 4 as well as the last page).

The code should be commented as in the previous lab.

Note (in the flow summary) how many logic elements were used.

Task 1b: Simulate the code to verify that it works as expected (i.e., generate a timing diagram).  Present these results neatly.  You don't need to show that each digit is represented correctly, but pick two or three numbers and show that the simulated result is as expected.

Task 1c: Connect the inputs to the four bits of a counter (E15Counter1HzB.v).  Display the four bits on LEDR[3:0] and verify for yourself  that the digit on HEX0  increments as expected.

Task 1d: Display the netlist to show the circuit you created in your module.  I ask you to do this just so you get an idea of the complexity of the circuits you are creating with some very basic Verilog code.

Write code that gets two four bit numbers as inputs.  The number on switches SW[3]-SW[0] should be displayed on Hex6 and is one input to the adder.  The number on switches SW[7]-SW[4] should be displayed on HEX7 and represents the other input.  The result should be on HEX5 and HEX4.

Note (in the flow summary) how many logic elements were used.

Repeat task 2 if the 4 bit inputs represent BCD digits, and use a BCD output (i.e., the two output digits should display a decimal number from 00 (0+0) to 18 (9+9).  You can assume all inputs are valid (i.e., the inputs are two numbers between 0 and 9).

### Task 4: Extras (not required)

Task 4a:  The counter in E15CounterSlow.v increments once every 16 seconds.  Load it to your work folder, and add it to your project.  Use it as one input to the adder, and the 1 Hz clock as the other input. The circuit should generate all possible one digit inputs and their sums.

Task 4b: Design a decoder that considers each number as a 4 bit two's complement number and displays the results on HEX7,HEX6 (HEX7 is minus sign (if needed), HEX6 is number).

Task 4c: Use switches as inputs but consider the number as two's complement.  Show the two numbers to be added on HEX7,HEX6 and HEX5,HEX4 (use HEX7 or HEX5 for minus sign, and HEX6 and HEX4 for the number).  Display result on HEX2, HEX1, HEX0 (HEX2=minus sign).

### To Turn in:

Each part of each task should be well labeled and in order.

• Task 1a:  (20 pts)  Turn in your code, neatly indented and thoroughly commented (as with your previous lab).  By "thoroughly commented" I mean that the comments should be sufficient that somebody with Verilog experience (but who is not in the class) could understand completely what you did.
• (5 pts) How many logic elements did your code use?
• Task 1b:  (15 pts)  Thorough and neatly presented results.  You don't need to show that each digit is represented correctly, but pick two or three numbers and show that the simulated result is as expected.
• Task 1c:  (10 pts)  Neatly indented and thoroughly commented Verilog code.  Demo to me.