E15 Laboratory 1

Digital Design with Schematics

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Task 0: Quartus tutorial for schematic entry

Go through the tutorial describing schematic entry in Quartus and downloading designs to the DE2 board.

Task 1: Simulating a die (singular of dice)

Assume you have seven LED's (light emitting diodes) as shown below:

Task 1a: Use truth tables and Karnaugh maps to design a circuit that lights up the LED's as shown (the input to the circuit should be the binary representation of the numbers 0-5). We don't care what happens when the count is 6 or 7.

Count₁₀	0	1	2	3	4	5
Count₂	000	001	010	011	100	101
LED's

Start by making a truth table with three inputs and four outputs as shown below (the output corresponding to LED "D" is completed). Then make four Karnaugh maps (one for each output), and simplify the expressions.

Decimal Equiv.	Inputs			Die Output	LED's
Decimal Equiv.	Q₂	Q₁	Q₀	Die Output	D	A, G	C, E	B, F
0	0	0	0	1	1
1	0	0	1	2	0
2	0	1	0	3	1
3	0	1	1	4	0
4	1	0	0	5	1
5	1	0	1	6	0
6	1	1	0	None	X
7	1	1	1	None	X

Task 1b: Plug in the "E15 I/O" board to the "Altera DE2" board in the slot label "GPIO1." Make sure the power jumper (just to the left to the grid of holes) is in the position marked "DE2."

Use Quartus to make a schematic that implements the design from above. Use only and and or gates (and inverters, as necessary, for the inputs). Set the three inputs to KEY[2], KEY[1] and KEY[0] (KEY[2] is MSB (Q₂), KEY[0] is LSB (Q₀)). Remember that the KEYs give a high output when unpressed, and a low output when pressed.

Set the outputs to the appropriate 7 LED's on the E15 I/O board. For reference, the pins are given below. The names in parentheses are defined in the file "E15DE2_IO.qsf", so you don't need to manually enter them.

LED 1 (Red):A DE2: PIN_N24 (LEDR_L)		LED 7 (Red):E DE2: PIN_T25 (LEDR_R)
LED 2 (Yellow):B DE2: PIN_R25 (LEDY_L)	LED 5 (Yellow):D DE2: PIN_T23 (LEDY_M)	LED 8 (Yellow):F DE2: PIN_T21 (LEDY_R)
LED 3 (Green):C DE2: PIN_R20 (LEDG_L)		LED 9 (Green):G DE2: PIN_U26 (LEDG_R)

When this is working, demonstrate it to me.

Just-for-grins: To see how Quartus actually implements your circuit go to Tools→Netlist Viewer→Technology Map Viewer (Pre-Fitting). You can expand blocks by double-clicking on them to see what is under them.

Note: for each task it is easiest to start a new project (using the same settings as before) and copy files from the old project as needed. Just doing a "Save as..." doesn't work (the new file is not automatically added to the project; nor is the old file removed). I can show you how to set things properly, but for this class it is generally easier just to start a new project. See "Common Problems" at end of Quartus Schematics Tutorial.

Task 1c: Add the files E15Counter1Hz.bsf and E15Counter1Hz.v to your working directory. This is a counter set to increment at 1 Hz. Add the part E15Counter1Hz to your schematic and set it to count from 0 to 5. Verify that it works.
Debugging hint: If your circuit doesn't work and the problem isn't obvious try connecting Q₂, Q₁ and Q₀ to LEDG[2], LEDG[1] and LEDG[0] so you can see what the inputs to your circuit are.

Task 1d: Add the files E15Cntr50MHz.bsf and E15Cntr50MHz.v to your working directory. This is a counter set to increment at 50 MHz. Use KEY[0] to enable (i.e., let through clock pulses) whenever it is pressed, and to disable (i.e., be at a constant value when it is released). Hint: use a two input gate, attach the oscillator "CLOCK_50" to one input, and "KEY[0]" to the other. The output of the gate should oscillate when "KEY[0]" is pushed, but not when it is released. Since the counter increments at 50 MHz, you should get effectively random outputs.

Task 1e: "Roll" your die 36 times and record the output. Compare to expected values.

Task 1f: Optional - complete the lab and come back to this. Can you get simpler circuits (determined by counting the total number of gate-inputs in your circuit, not including inverters) by changing which LED's are on for rolls of the die of "2" and "3" as shown below. Note the display of 1, 4, 5, 6 on the die are unchanged because of symmetry.

Count₁₀	0	1	2	3	4	5
Count₂	000	001	010	011	100	101
Default
Option 1
Option 2
Option 3

Task 1g: Optional - complete the lab and come back to this. Can you get simpler circuits (determined by counting the total number of gate-inputs) by also changing the order of the outputs (which for our purposes is arbitrary)? An example is given below. It is probably too difficult to try all options, so you may have to think about some heuristic. I'll give more points for circuits that are simpler.

(Note: in option 1, I moved "6" to the 0 column so the two side LED's are only lit when all three inputs are 0 (i.e., a 3 input nand gate). In option 2, I moved "6" to the 3 column so the two side LED's are lit when the two LSB's are 1 (i.e., a 2 input nand gate followed by an inverter (which is a 1 input nand gate))).

Count₁₀	0	1	2	3	4	5
Count₂	000	001	010	011	100	101
Default
Option 1
Option 2
Option 3	...

Task 1h: Optional - complete the lab and come back to this. Use Karnaugh maps to design a loaded die (i.e, one with unequal probablities). The numbers 2, 3, 4, 5, and 6 should appear 5 out of 32 throws, but the number 1 should appear 7 out of 32 throws. You don't need to build the design, but give your minimum sum-of-products equations and sketch the circuit.

Task 2: A Stoplight.

Design a traffic light controller using Quartus and testing it by programming the Altera board. To do so, you will design a combinational circuit that takes as input a 4-bit binary number and outputs the proper traffic light signals for a 4-way intersection (6 outputs). Your inputs should come from the 1 Hz counter you used previously. The outputs should be the outer two columns of LED's on the E15 I/O board.

The signals should change according to the following table:

Input Values	Light Setting
Input Values	North-South	East-West
0-5	Red	Green
6-7	Red	Yellow
8	Red	Red
9-12	Green	Red
13-14	Yellow	Red
15	Red	Red

Task 2a: Complete truth tables and Karnaugh maps and develop minimum sum-of-products forms for each output.

Task 2b: Use Quartus to make a schematic that implements the design from above. Use only nand gates (and inverters, as necessary, for the inputs). Going from and and or gates to all nand is easy with De Morgan's theorem. Ask me if you are unclear as to how to procede.

Task 2c: Demonstrate your circuit to me when driven by the 1 Hz counter.
Debugging hint: If your circuit doesn't work and the problem isn't obvious try connecting Q₃→Q₀ to LEDG[3]→LEDG[0] so you can see what the inputs to your circuit are.

(If you want to, you can load the program on the DE2 board (see "Active Serial Programming") and run your code with the stop-lights in Hicks 310 - but we'll be doing this in the next lab anyway).

Task 2d: Optional - complete the lab and come back to this. At some intersections of a busy road and one that is not very busy, the light stays green on the busy road until a car shows up on the other road, at which time the light changes. Let the East-West road be the busy road. Have your circuit stay at count 0 (East-West is green, North-South is red) until KEY[0] is pressed for a while (indicating a car on the North-South road), at which time the circuit goes through a complete cycle.

Design such a circuit.

Task 2e: Implement and demonstrate the circuit to me.

Task 2f: Optional - complete the lab and come back to this. Determine a minimum product-of-sum forms for the stop-light system (i.e., repeat Task 2a for product-of-sums).

To Turn in:

The grading of each subtask is as follows.

Task 1
- Task 1a: (20 pts) The completed truth tables and Karnaugh maps and sum-of-products equations.
- Task 1b: (5 pts) Demo to me - nothing written.
- Task 1c: (15 pts) The Quartus schematic (and and or gates only) with the 1 Hz counter.
- Task 1d: (10 pts) The Quartus schematic with the 50 MHz gated counter.
- Task 1e: (5 pts) The results of 36 rolls of the die.
- Task 1f: (5 pts - Optional) A clear, concise, and correct argument about which option is simplest (along with Karnaugh maps and circuit diagrams). State explicitly how many many gate-inputs your system has.
- Task 1g: (5 pts max (more points for simpler designs) - Optional) A clear, concise presentation of a simpler arrangement and a short (1 or 2 paragraph) distinction of your design method (along with Karnaugh maps and circuit diagrams). State explicitly how many many gate-inputs your system has.
- Task 1h: (5 pts - Optional) Give Karnaugh maps and sum-of-products equations.
Task 2
- Task 2a: (20 pts) The completed truth tables and Karnaugh maps and sum-of-products equations.
- Task 2b: (20 pts) The Quartus schematic (nand gates only) with the 1 Hz counter..
- Task 2c: (5 pts) Demo to me - nothing written.
- Task 2d: (5 pts - Optional) Schematic diagram and short (1 paragraph) description of how your circuit works.
- Task 2e: (5 pts - Optional) Demo to me - nothing written
- Task 2f: (5 pts - Optional) Give a minimum product of sums form (including Karnaugh maps) for the stop-light system.

This is a minimal list, feel free to augment with material you think is necessary (but I'm not looking for anything beyond what I ask for).

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Please contact me if you find any errors or other problems (e.g., something is unclearly stated) in this web page