module E15Counter1Hz(input Clk, D3, D2, D1, D0, output Q3, Q2, Q1, Q0);

reg [25:0]R;
reg [3:0]CntOut;
wire [3:0]MaxCnt;
assign {Q3, Q2, Q1, Q0}=CntOut;
assign MaxCnt={D3, D2, D1, D0};

always @(posedge Clk)
begin
	if (R<50000000)
		R <= R+26'b1;
	else
		begin
			R <= 26'b0;
			CntOut <= ((CntOut<MaxCnt) ? CntOut+4'b1 : 4'b0);
		end
end

endmodule